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Dual, 8-/10-/12-/14-Bit Low Power Digital-to-Analog Converters AD9714/AD9715/AD9716/AD9717
FEATURES
Power dissipation @ 3.3 V, 2 mA output 37 mW @ 10 MSPS 80 mW @ 125 MSPS Sleep mode: <3 mW @ 3.3 V Supply voltage: 1.8 V to 3.3 V SFDR to Nyquist 84 dBc @ 1 MHz output 75 dBc @ 10 MHz output AD9717 NSD @ 1 MHz output, 125 MSPS, 2 mA: -151 dBc/Hz Differential current outputs: 1 mA to 4 mA Two on-chip auxiliary DACs CMOS inputs with single-port operation Output common mode: adjustable 0 V to 1.2 V Small footprint 40-lead LFCSP Pb-free package
GENERAL DESCRIPTION
The AD9714/AD9715/AD9716/AD9717 are pin-compatible dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC(R) converters are optimized for the transmit signal path of communication systems. All the devices share the same interface, LFCSP package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9714/AD9715/AD9716/AD9717 offer exceptional ac and dc performance and support update rates up to 125 MSPS. The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9714/AD9715/AD9716/AD9717 make them well-suited for portable and low power applications.
PRODUCT HIGHLIGHTS
1. Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power consumption reduces to 35 mW at 125 MSPS with a 1.8 V supply. Sleep and power-down modes are provided for low power idle periods. CMOS Clock Input. High speed, single-ended CMOS clock input supports 125 MSPS conversion rate. Easy Interfacing to Other Components. Adjustable output common mode from 0 V to 1.2 V allows for easy interfacing to other components that accept commonmode levels greater than 0 V.
APPLICATIONS
Wireless infrastructures Picocell, femtocell base stations Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators
2.
3.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD9714/AD9715/AD9716/AD9717 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 Digital Specifications ................................................................... 6 AC Specifications.......................................................................... 7 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 17 Terminology .................................................................................... 29 Theory of Operation ...................................................................... 30 Serial Peripheral Interface (SPI) ................................................... 31 General Operation of the Serial Interface ............................... 31 Instruction Byte .......................................................................... 31 Serial Interface Port Pin Descriptions ..................................... 31 MSB/LSB Transfers..................................................................... 32 Serial Port Operation ................................................................. 32 Pin Mode ..................................................................................... 32 SPI Register Map ............................................................................ 33 SPI Register Descriptions .............................................................. 34 Digital Interface Operation ........................................................... 37 Digital Data Latching and Retimer Section ............................ 38 Estimating the Overall DAC Pipeline Delay........................... 39 Self-Calibration........................................................................... 40 Coarse Gain Adjustment ........................................................... 41 Using the Internal Termination Resistors ............................... 42 Applications Information .............................................................. 43 Output Configurations .............................................................. 43 Differential Coupling Using a Transformer ............................... 43 Single-Ended Buffered Output Using an Op Amp ................ 43 Differential Buffered Output Using an Op Amp ................... 44 Auxiliary DACs........................................................................... 44 DAC-to-Modulator Interfacing ................................................ 45 Correcting for Nonideal Performance of Quadrature Modulators on the IF-to-RF Conversion ................................ 45 I/Q Channel Gain Matching ..................................................... 45 LO Feedthrough Compensation .............................................. 46 Results of Gain and Offset Correction .................................... 46 Modifying the Evaluation Board to Use the ADL5370 On-Board Quadrature Modulator ........................................... 47 Outline Dimensions ....................................................................... 48 Ordering Guide .......................................................................... 48
REVISION HISTORY
8/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 48
AD9714/AD9715/AD9716/AD9717 FUNCTIONAL BLOCK DIAGRAM
FSADJQ/AUXQ SDIO/FORMAT RESET/PINMD SCLK/CLKMD FSADJI/AUXI DB13 (MSB) CS/PWRDN REFIO DB12 CMLI
1V DB11 DB10 DB9 DB8 DVDDIO DVSS DVDD DB7 DB6 DB5 CLOCK DIST 1.8V LDO IREF 100A BAND GAP 1 INTO 2 INTERLEAVED DATA INTERFACE I DATA SPI INTERFACE RSET 16k 10k
AD9714/AD9715/ AD9716/AD9717
RSET 16k RCM 1k TO 250
RLIN 500 IOUTN IOUTP 500 RLIP AVDD AVSS RLQP 500
I DAC
AUX1DAC
AUX2DAC
Q DATA
Q DAC 500
QOUTP QOUTN RLQN
RCM 1k TO 250
DCLKIO
CLKIN
DB0 (LSB)
CMLQ
CVDD
CVSS
DB4
DB3
DB2
DB1
Figure 1.
Rev. 0 | Page 3 of 48
07265-001
AD9714/AD9715/AD9716/AD9717 SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IOUTFS = 2 mA, maximum sample rate, unless otherwise noted. Table 1.
Parameter RESOLUTION ACCURACY @ 3.3 V Differential Nonlinearity (DNL) Precalibration Postcalibration Integral Nonlinearity (INL) Precalibration Postcalibration ACCURACY @ 1.8 V Differential Nonlinearity (DNL) Precalibration Postcalibration Integral Nonlinearity (INL) Precalibration Postcalibration MAIN DAC OUTPUTS Offset Error Gain Error Internal Reference Full-Scale Output Current 1 VCC = 3.3 V VCC = 1.8 V Output Compliance Range Output Resistance Crosstalk, Q DAC to I DAC fOUT = 30 MHz fOUT = 60 MHz MAIN DAC TEMPERATURE DRIFT Offset Gain Reference Voltage AUXDAC OUTPUTS Resolution Full-Scale Output Current (Current Sourcing Mode) Voltage Output Mode Output Compliance Range (Sourcing 1 mA) Output Compliance Range (Sinking 1 mA) Output Resistance in Current Output Mode VSS to +1 V AUX DAC Monotonicity Guaranteed REFERENCE OUTPUT Internal Reference Voltage Output Resistance REFERENCE INPUT Voltage Compliance Input Resistance Min AD9714 Typ Max 8 Min AD9715 Typ Max 10 Min AD9716 Typ Max 12 Min AD9717 Typ Max 14 Unit Bits
0.02 0.003 0.025 0.01
0.08 0.01 0.13 0.05
0.4 0.2 0.4 0.3
1.7 1.0 1.8 1.3
LSB LSB LSB LSB
0.02 0.005 0.025 0.02 -1 -2 1 1 -0.5 2 2 0 200 97 78 0 40 25 10 125 VSS VSS VSS + 0.25 1 10 VDD VDD - 0.25 VDD VSS VSS VSS + 0.25 0 +1 +2 4 2.5 +1.2 -1 -2 1 1 -0.5
0.08 0.01 0.12 0.05 0 +1 +2 2 2 0 200 97 78 0 40 25 10 125 VDD VDD - 0.25 VDD 1 10 VSS VSS VSS + 0.25 4 2.5 +1.2 -1 -2 1 1 -0.5
0.4 0.2 0.4 0.25 0 +1 +2 2 2 0 200 97 78 0 40 25 10 125 VDD VDD - 0.25 VDD 1 10 VSS VSS VSS + 0.25 4 2.5 +1.2 -1 -2 1 1 -0.5
1.2 1.0 1.5 1.1 0 +1 +2 2 2 0 200 97 78 0 40 25 10 125 VDD VDD - 0.25 VDD 1 10 4 2.5 +1.2
LSB LSB LSB LSB mV % of FSR mA mA V M dB dB ppm/C ppm/C ppm/C Bits A V V V M Bits
0.98
1.025 10
1.08
0.98
1.025 10
1.08
0.98
1.025 10
1.08
0.98
1.025 10
1.08
V k V M
0.1 1
1.25
0.1 1
1.25
0.1 1
1.25
0.1 1
1.25
Rev. 0 | Page 4 of 48
AD9714/AD9715/AD9716/AD9717
Parameter DAC MATCHING Gain Matching ANALOG SUPPLY VOLTAGES AVDD CVDD DIGITAL SUPPLY VOLTAGES DVDD DVDDIO POWER CONSUMPTION @ 3.3 V fDAC = 125 MSPS, IF = 12.5 MHz IAVDD IDVDD 2 IDVDDIO 3 ICVDD Power-Down Mode with Clock Power-Down Mode No Clock Power Supply Rejection Ratio POWER CONSUMPTION @ 1.8 V fDAC = 125 MSPS, IF = 12.5 MHz IAVDD IDVDD + IDVDDIO ICVDD Power-Down Mode with Clock Power-Down Mode No Clock Power Supply Rejection Ratio OPERATING RANGE
1 2
Min -1 1.7 1.7 1.7 1.7
AD9714 Typ Max +1 3.5 3.5 1.9 3.5 86 10 0 11 3 50 1.5 -0.04 35 10 8 1.5 12 850 -0.001 +25
Min -1 1.7 1.7 1.7 1.7
AD9715 Typ Max +1 3.5 3.5 1.9 3.5 86 10 0 11 3 50 1.5 -0.04 35 10 8 1.5 12 850 -0.001 +25
Min -1 1.7 1.7 1.7 1.7
AD9716 Typ Max +1 3.5 3.5 1.9 3.5 86 10 0 11 3 50 1.5 -0.04 35 10 8 1.5 12 850 -0.001 +25
Min -1 1.7 1.7 1.7 1.7
AD9717 Typ Max +1 3.5 3.5 1.9 3.5 86 10 0 11 3 50 1.5 -0.04 35 10 8 1.5 12 850 -0.001 +25
Unit % FSR V V V V mW mA mA mA mA mW mW % FSR/V mW mA mA mA mW W % FSR/V C
-40
+85
-40
+85
-40
+85
-40
+85
Based on a 10 k external resistor. Bypass only. 3 LDO on.
Rev. 0 | Page 5 of 48
AD9714/AD9715/AD9716/AD9717
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IOUTFS = 2 mA, maximum sample rate, unless otherwise noted. Table 2.
Parameter DAC CLOCK INPUT (CLKIN) VIH VIL Maximum Clock Rate SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) Minimum Pulse Width High Minimum Pulse Width Low INPUT DATA 1.8 V Q-Channel or DCLKIO Falling Edge Setup Hold I-Channel or DCLKIO Rising Edge Setup Hold 3.3 V Q-Channel or DCLKIO Falling Edge Setup Hold I-Channel or DCLKIO Rising Edge Setup Hold VIH VIL Min 2.1 Typ 3 0 Max Unit V V MSPS MHz ns ns
0.9 125
25 20 20
0.25 1.2 0.13 1.1 -0.2 1.5 -0.2 1.6 3 0
ns ns ns ns ns ns ns ns V V
2.1
0.9
Rev. 0 | Page 6 of 48
AD9714/AD9715/AD9716/AD9717
AC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, DVDDIO = 1.8 V, CVDD = 3.3 V, IOUTFS = 2 mA, maximum sample rate, unless otherwise noted. Table 3.
Parameter SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 125 MSPS, fOUT = 10 MHz fDAC = 125 MSPS, fOUT = 50 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 125 MSPS, fOUT = 10 MHz fDAC = 125 MSPS, fOUT = 50 MHz NOISE SPECTRAL DENSITY (NSD) EIGHTTONE, 500 kHz TONE SPACING fDAC = 125 MSPS, fOUT = 10 MHz fDAC = 125 MSPS, fOUT = 50 MHz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 61.44 MSPS, fOUT = 20 MHz fDAC = 122.88 MSPS, fOUT = 30 MHz Min AD9714 Typ Max 75 60 Min AD9715 Typ Max 82 61 Min AD9716 Typ Max 83 62 Min AD9717 Typ Max 84 63 Unit dBc dBc
86 71
87 71
88 71
89 71
dBc dBc
-129 -123
-141 -135
-149 -137
-152 -141
dBc/Hz dBc/Hz
-71 -72
-71 -72
-71 -72
-71 -72
dBc dBc
TMIN to TMAX, AVDD = 1.8 V, DVDD = 3.3 V, DVDDIO = 1.8 V, CVDD = 3.3 V, IOUTFS = 2 mA, maximum sample rate, unless otherwise noted. Table 4.
Parameter SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 125 MSPS, fOUT = 10 MHz fDAC = 125 MSPS, fOUT = 50 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 125 MSPS, fOUT = 10 MHz fDAC = 125 MSPS, fOUT = 50 MHz NOISE SPECTRAL DENSITY (NSD) EIGHTTONE, 500 kHz TONE SPACING fDAC = 125 MSPS, fOUT = 10 MHz fDAC = 125 MSPS, fOUT = 50 MHz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 61.44 MSPS, fOUT = 20 MHz fDAC = 122.88 MSPS, fOUT = 30 MHz Min AD9714 Typ Max 75 55 Min AD9715 Typ Max 78 56 Min AD9716 Typ Max 79 57 Min AD9717 Typ Max 80 58 Unit dBc dBc
79 53
80 53
84 53
85 53
dBc dBc
-132 -126
-141 -131
-146 -131
-148 -132
dBc/Hz dBc/Hz
-68 -68
-68 -68
-68 -68
-68 -68
dBc dBc
Rev. 0 | Page 7 of 48
AD9714/AD9715/AD9716/AD9717 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter AVDD, DVDDIO, CVDD to AVSS, DVSS, CVSS DVDD to DVSS AVSS to DVSS, CVSS DVSS to AVSS, CVSS CVSS to AVSS, DVSS VREF, FSADJQ, FSADJI, CMLQ, CMLI to AVSS QOUTP, QOUTN, IOUTP, IOUTN, RLQP, RLQN, RLIP, RLIN to AVSS D13 to D0, CS, SCLK, SDIO, SDO, RESET to DVSS CLKIN to CVSS CS, SCLK, SDIO, SDO to DVSS Junction Temperature Storage Temperature Range Rating -0.3 V to +3.9 V -0.3 V to +2.1 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to AVDD + 0.3 V -1.0 V to AVDD + 0.3 V -0.3 V to DVDD + 0.3 V -0.3 V to CVDD + 0.3 V -0.3 V to DVDD + 0.3 V 125C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
Table 6.
Package Type 40-Lead LFCSP (With No Airflow Movement) JA 29.8 Unit C/W
ESD CAUTION
Rev. 0 | Page 8 of 48
AD9714/AD9715/AD9716/AD9717 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DB12 DB13 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI
DB11 1 DB10 2 DB9 3 DB8 4 DVDDIO 5 DVSS 6 DVDD 7 DB7 8 DB6 9 DB5 10
40 39 38 37 36 35 34 33 32 31
PIN 1 INDICATOR
AD9717
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN
NOTES 1. THE HEAT SINK PAD IS CONNECTED TO AVSS AND SHOULD BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD.
DB4 DB3 DB2 DB1 DB0 (LSB) DCLKIO CVDD CLKIN CVSS CMLQ
11 12 13 14 15 16 17 18 19 20
Figure 2. AD9717 Pin Configuration
Table 7. AD9717 Pin Function Descriptions
Pin No. 1 to 4 5 6 7 8 to 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Mnemonic DB[11:8] DVDDIO DVSS DVDD DB[7:1] DB0 (LSB) DCLKIO CVDD CLKIN CVSS CMLQ RLQN QOUTN QOUTP RLQP AVSS AVDD RLIP IOUTP IOUTN RLIN CMLI FSADJQ/AUXQ Description Digital Inputs. Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). Digital Common. Digital Core Supply Voltage (1.8 V). Provides a 1.8 V output when the internal LDO regulator is enabled. Digital Inputs. Digital Input (LSB). Data Input/Output Clock. Clock used to qualify input data. Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be DVDD. LVCMOS Sampling Clock Input. Sampling Clock Supply Voltage Common. Q DAC Output Common-Mode Level. Load Resistor (500 ) to the CMLQ Pin. Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. Load Resistor (500 ) to the CMLQ Pin. Analog Common. Analog Supply Voltage (1.8 V to 3.3 V). Load Resistor (500 ) to the CMLI Pin. Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. I DAC Current Output. Full-scale current is sourced when all data bits are 1s. Load Resistor (500 ) to the CMLI Pin. I DAC Output Common-Mode Level. Full-Scale Current Output Adjust for Q DAC. Connect to AVSS through a resistor. Auxiliary Q DAC. The pin becomes the output of an optional, serial port driven, auxiliary DAC when the internal on-chip, RSET, is enabled. Full-Scale Current Output Adjust for I DAC. Connect to AVSS through a resistor. Auxiliary I DAC. The pin becomes the output of an optional, serial port driven, auxiliary DAC when the internal on-chip, RSET, is enabled. Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 F capacitor to AVSS is required).
33
FSADJI/AUXI
34
REFIO
Rev. 0 | Page 9 of 48
07265-002
AD9714/AD9715/AD9716/AD9717
Pin No. 35 36 Mnemonic RESET/PINMD SCLK/CLKMD Description Reset. In SPI mode, pulse RESET high to reset SPI registers to default values. Pin Mode. A constant Logic 1 puts the device into pin mode. Serial Clock. Clock input for serial port in spi mode Clock Mode. In pin mode, CLKMD determines phase of internal retiming clock. DCLKIO = CLKIN: Tie to 0. DCLKIO CLKIN: Pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). Serial Port Input/Output. Bidirectional data line for serial port in spi mode. Data Format. In pin mode, FORMAT determines data format of digital data. Chip Select. Active low chip select in spi mode. Power Down. In pin mode, PWRDN powers down the device except for the SPI port. Digital Input (MSB). Digital Input. The heat sink pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at package corners is connected to this pad.
37 38 39 40
SDIO/FORMAT CS/PWRDN DB13 (MSB) DB12 Heat Sink Pad
Rev. 0 | Page 10 of 48
AD9714/AD9715/AD9716/AD9717
DB10 DB11 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI
DB9 1 DB8 2 DB7 3 DB6 4 DVDDIO 5 DVSS 6 DVDD 7 DB5 8 DB4 9 DB3 10
40 39 38 37 36 35 34 33 32 31
PIN 1 INDICATOR
AD9716
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
RLIN IOUTN IOUTP RL2P AVDD AVSS RLQP QOUTP QOUTN RLQN
NOTES 1. NC = NO CONNECT 2. THE HEAT SINK PAD IS CONNECTED TO AVSS AND SHOULD BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD.
DB2 DB1 DB0 (LSB) NC NC DCLKIO CVDD CLKIN CVSS CMLQ
11 12 13 14 15 16 17 18 19 20
Figure 3. AD9716 Pin Configuration
Table 8. AD9716 Pin Function Descriptions
Pin No. 1 to 4 5 6 7 8 to 12 13 14,15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Mnemonic DB[9:6] DVDDIO DVSS DVDD DB[5:1] DB0 (LSB) NC DCLKIO CVDD CLKIN CVSS CMLQ RLQN QOUTN QOUTP RLQP AVSS AVDD RL2P IOUTP IOUTN RLIN CMLI FSADJQ/AUXQ Description Digital Inputs. Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). Digital Common. Digital Core Supply Voltage (1.8 V). Provides a 1.8 V output when in internal LDO regulator is enabled. Digital Inputs. Digital Input (LSB). No Connect. These pins are not connected to the chip. Data Input Clock. Used to clock data in from digital source. Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be DVDD. Sampling Clock Input. Sampling Clock Supply Voltage Common. Q DAC Output Common-Mode Level. Load Resistor (500 ) to the CMLQ Pin. Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. Load Resistor (500 ) to the CMLQ Pin. Analog Common. Analog Supply Voltage (1.8 V to 3.3 V). Load Resistor (500 ) to the CMLI Pin. Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. I DAC Current Output. Full-scale current is sourced when all data bits are 1s. Load Resistor (500 ) to the CMLI Pin. I DAC Output Common-Mode Level. Full-Scale Current Output Adjust for Q DAC. Connect to AVSS through a resistor. Auxiliary Q DAC. The pin becomes the output of an optional, serial port driven, auxiliary DAC when the internal on-chip, RSET, is enabled. Full-Scale Current Output Adjust for I DAC. Connect to AVSS through a resistor. Auxiliary I DAC. The pin becomes the output of an optional, serial port driven, auxiliary DAC when the internal on-chip, RSET, is enabled. Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 F capacitor to AVSS is required).
33
FSADJI/AUXI
34
REFIO
Rev. 0 | Page 11 of 48
07265-003
AD9714/AD9715/AD9716/AD9717
Pin No. 35 36 Mnemonic RESET/PINMD SCLK/CLKMD Description Reset in SPI Mode. Pulse high to reset SPI registers to default values. Pin Mode. A constant Logic 1 puts the device into pin mode. Serial Clock. Clock input for serial port in spi mode. Clock Mode. In pin mode, CLKMD determines phase of internal retiming clock. DCLKIO = CLKIN: Tie to 0. DCLKIO CLKIN: Pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). Serial Port Input/Output. Bidirectional data line for serial port in spi mode. Data Format. In pin mode, FORMAT determines data format of digital data. Chip Select. Active low chip select in spi mode. Power Down. In pin mode, PWRDN powers down the device except for the SPI port. Digital Input (MSB). Digital Input. The heat sink pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at package corners is connected to this pad.
37 38 39 40
SDIO/FORMAT CS/PWRDN DB11 (MSB) DB10 Heat Sink Pad
Rev. 0 | Page 12 of 48
AD9714/AD9715/AD9716/AD9717
DB8 DB9 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI 40 39 38 37 36 35 34 33 32 31
PIN 1 INDICATOR
DB7 1 DB6 2 DB5 3 DB4 4 DVDDIO 5 DVSS 6 DVDD 7 DB3 8 DB2 9 DB1 10
AD9715
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
RLIN IOUTP IOUTN RL2N AVDD AVSS RL1P QOUTP QOUTN RL1N
NOTES 1. NC = NO CONNECT 2. THE HEAT SINK PAD IS CONNECTED TO AVSS AND SHOULD BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD.
DB0 (LSB) NC NC NC NC DCLKIO CVDD CLKIN CVSS CMLQ
11 12 13 14 15 16 17 18 19 20
Figure 4. AD9715 Pin Configuration
Table 9. AD9715 Pin Function Descriptions
Pin No. 1 to 4 5 6 7 8 to 10 11 12 to 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Mnemonic DB[7:4] DVDDIO DVSS DVDD DB[3:1] DB0 (LSB) NC DCLKIO CVDD CLKIN CVSS CMLQ RL1N QOUTN QOUTP RL1P AVSS AVDD RL2N IOUTN IOUTP RLIN CMLI FSADJQ/AUXQ Description Digital Inputs. Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). Digital Common. Digital Core Supply Voltage (1.8 V). Provides a 1.8 V output when in internal LDO regulator is enabled. Digital Inputs. Digital Input (LSB). No Connect. These pins are not connected to the chip. Data Input Clock. Used to clock data in from digital source. Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be DVDD. Sampling Clock Input. Sampling Clock Supply Voltage Common. Q DAC Output Common-Mode Level. Load Resistor (500 ) to the CMLQ Pin. Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. Load Resistor (500 ) to the CMLQ Pin. Analog Common. Analog Supply Voltage (1.8 V to 3.3 V). Load Resistor (500 ) to the CMLI Pin. Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. I DAC Current Output. Full-scale current is sourced when all data bits are 1s. Load Resistor (500 ) to the CMLI Pin. I DAC Output Common-Mode Level. Full-Scale Current Output Adjust for Q DAC. Connect to AVSS through a resistor. Auxiliary Q DAC. The pin becomes the output of an optional, serial port driven, auxiliary DAC when the internal on-chip, RSET, is enabled. Full-Scale Current Output Adjust for I DAC. Connect to AVSS through a resistor. Auxiliary I DAC. The pin becomes the output of an optional, serial port driven, auxiliary DAC when the internal on-chip, RSET, is enabled. Reference Input/Output. Serves as reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 F capacitor to AVSS is required).
33
FSADJI/AUXI
34
REFIO
Rev. 0 | Page 13 of 48
07265-067
AD9714/AD9715/AD9716/AD9717
Pin No. 35 36 Mnemonic RESET/PINMD SCLK/CLKMD Description Reset in SPI Mode. Pulse high to reset SPI registers to default values. Pin Mode. A constant Logic 1 puts device into pin mode. Serial Clock. Clock input for serial port in spi mode. Clock Mode. In pin mode, CLKMD determines phase of internal retiming clock. DCLKIO = CLKIN: Tie to 0. DCLKIO CLKIN: Pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). Serial Port Input/Output. Bidirectional data line for serial port in spi mode. Data Format. In pin mode, FORMAT determines data format of digital data. Chip Select. Active low chip select in spi mode. Power Down. In pin mode, PWRDN powers down the device except for the SPI port. Digital Input (MSB). Digital Input. The heat sink pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at package corners is connected to this pad.
37 38 39 40
SDIO/FORMAT CS/PWRDN DB9 (MSB) DB8 Heat Sink Pad
Rev. 0 | Page 14 of 48
AD9714/AD9715/AD9716/AD9717
DB6 DB7 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI 40 39 38 37 36 35 34 33 32 31
DB5 1 DB4 2 DB3 3 DB2 4 DVDDIO 5 DVSS 6 DVDD 7 DB1 8 DB0 (LSB) 9 NC 10
PIN 1 INDICATOR
AD9714
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
RLIN IOUTP IOUTN RL2N AVDD AVSS RL1P QOUTP QOUTN RL1N
NOTES 1. NC = NO CONNECT 2. THE HEAT SINK PAD IS CONNECTED TO AVSS AND SHOULD BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD.
NC NC NC NC NC DCLKIO CVDD CLKIN CVSS CMLQ
11 12 13 14 15 16 17 18 19 20
Figure 5. AD9714 Pin Configuration
Table 10. AD9714 Pin Function Descriptions
Pin No. 1 to 4 5 6 7 8 9 10 to 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Mnemonic DB[5:2] DVDDIO DVSS DVDD DB1 DB0 (LSB) NC DCLKIO CVDD CLKIN CVSS CMLQ RL1N QOUTN QOUTP RL1P AVSS AVDD RL2N IOUTN IOUTP RLIN CMLI FSADJQ/AUXQ Description Digital Inputs. Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). Digital Common. Digital Core Supply Voltage (1.8 V). Provides a 1.8 V output when the internal LDO regulator is enabled. Digital Inputs. Digital Input (LSB). No Connect. These pins are not connected to the chip. Data Input Clock. Used to clock data in from digital source. Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be DVDD. Sampling Clock Input. Sampling Clock Supply Voltage Common. Q DAC Output Common-Mode Level. Load Resistor (500 ) to the CMLQ Pin. Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. Load Resistor (500 ) to the CMLQ Pin. Analog Common. Analog Supply Voltage (1.8 V to 3.3 V). Load Resistor (500 ) to the CMLI Pin. Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. I DAC Current Output. Full-scale current is sourced when all data bits are 1s. Load Resistor (500 ) to the CMLI Pin. I DAC Output Common-Mode Level. Full-Scale Current Output Adjust for Q DAC. Connect to AVSS through a resistor. Auxiliary Q DAC. The pin becomes the output of an optional, serial port driven, auxiliary DAC when the internal on-chip, RSET, is enabled. Full-Scale Current Output Adjust for I DAC. Connect to AVSS through a resistor. Auxiliary I DAC. The pin becomes the output of an optional, serial port driven, auxiliary DAC when the internal on-chip, RSET, is enabled. Reference Input/Output. Serves as reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 F capacitor to AVSS is required).
33
FSADJI/AUXI
34
REFIO
Rev. 0 | Page 15 of 48
07265-066
AD9714/AD9715/AD9716/AD9717
Pin No. 35 36 Mnemonic RESET/PINMD SCLK/CLKMD Description Reset in SPI Mode. Pulse high to reset SPI registers to default values. Pin Mode. A constant Logic 1 puts device into pin mode. Serial Clock. Clock input for serial port in spi mode. Clock Mode. In pin mode, CLKMD determines phase of internal retiming clock. DCLKIO = CLKIN: Tie to 0. DCLKIO CLKIN: Pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). Serial Port Input/Output. Bidirectional data line for serial port in spi mode. Data Format. In pin mode, FORMAT determines data format of digital data. Chip Select. Active low chip select in spi mode. Power Down. In pin mode, PWRDN powers down the device except for the SPI port. Digital Input (MSB). Digital Input. The heat sink pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at package corners is connected to this pad.
37 38 39 40
SDIO/FORMAT CS/PWRDN DB7 (MSB) DB6 Heat Sink Pad
Rev. 0 | Page 16 of 48
AD9714/AD9715/AD9716/AD9717 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD, DVDD, DVDDIO, CVDD = 1.8 V, IOUTFS = 2 mA, maximum sample rate, unless otherwise noted.
1.5 1.5
1.0
1.0
0.5
POSTCALIBRATION INL (LSB)
07265-004
PRECALIBRATION INL (LSB)
0.5
0
0
-0.5
-0.5
-1.0
-1.0
0
2048
4096
6144
8192 10240 12288 CODE
14336 16384
0
2048
4096
6144
8192 10240 12288 CODE
14336 16384
Figure 6. AD9717 Precalibration INL at 1.8 V
Figure 9. AD9717 Postcalibration INL at 1.8 V
1.5
1.5
1.0
1.0
0.5
POSTCALIBRATION DNL (LSB)
PRECALIBRATION DNL (LSB)
0.5
0
0
-0.5
-0.5
-1.0
-1.0
07265-005
0
2048
4096
6144
8192 10240 12288 CODE
14336 16384
0
2048
4096
6144
8192 10240 12288 CODE
14336 16384
Figure 7. AD9717 Precalibration DNL at 1.8 V
1.75 1.25 0.75 0.25 -0.25 -0.75 -1.25 -1.75 1.75 1.25
Figure 10. AD9717 Postcalibration DNL at 1.8 V
POSTCALIBRATION INL (LSB)
PRECALIBRATION INL (LSB)
0.75 0.25 -0.25 -0.75 -1.25 -1.75
07265-006
0
2048
4096
6144
8192 10240 12288 CODE
14336 16384
0
2048
4096
6144
8192 10240 12288 CODE
14336 16384
Figure 8. AD9717 Precalibration INL at 3.3 V
Figure 11. AD9717 Postcalibration INL at 3.3 V
Rev. 0 | Page 17 of 48
07265-009
07265-008
-1.5
-1.5
07265-007
-1.5
-1.5
AD9714/AD9715/AD9716/AD9717
1.75 1.25 0.75 0.25 -0.25 -0.75 -1.25 -1.75 1.75 1.25
POSTCALIBRATION DNL (LSB)
07265-010
PRECALIBRATION DNL (LSB)
0.75 0.25 -0.25 -0.75 -1.25 -1.75
0
2048
4096
6144
8192 10240 12288 CODE
14336 16384
0
2048
4096
6144
8192 10240 12288 CODE
14336 16384
Figure 12. AD9717 Precalibration DNL at 3.3 V
Figure 15. AD9717 Postcalibration DNL at 3.3 V
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3
07265-011
0.4 0.3 POSTCALIBRATION INL (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3
07265-014 07265-015
PRECALIBRATION INL (LSB)
-0.4
0
512
1024
1536
2048 CODE
2560
3072
3584
4096
-0.4
0
512
1024
1536
2048 CODE
2560
3072
3584
4096
Figure 13. AD9716 Precalibration INL at 1.8 V
Figure 16. AD9716 Postcalibration INL at 1.8 V
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3
07265-012
0.4 0.3 POSTCALIBRATION DNL (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
PRECALIBRATION DNL (LSB)
-0.4
0
512
1024
1536
2048 CODE
2560
3072
3584
4096
0
512
1024
1536
2048 CODE
2560
3072
3584
4096
Figure 14. AD9716 Precalibration DNL at 1.8 V
Figure 17. AD9716 Postcalibration DNL at 1.8 V
Rev. 0 | Page 18 of 48
07265-013
AD9714/AD9715/AD9716/AD9717
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3
07265-016
0.4 0.3 POSTCALIBRATION INL (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3
07265-019 07265-021 07265-020
PRECALIBRATION INL (LSB)
-0.4
0
512
1024
1536
2048 CODE
2560
3072
3584
4096
-0.4
0
512
1024
1536
2048 CODE
2560
3072
3584
4098
Figure 18. AD9716 Precalibration INL at 3.3 V
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3
07265-017
Figure 21. AD9716 Postcalibration INL at 3.3 V
0.4 0.3 POSTCALIBRATION DNL (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
PRECALIBRATION DNL (LSB)
-0.4
0
512
1024
1536
2048 CODE
2560
3072
3584
4096
0
512
1024
1536
2048 CODE
2560
3072
3584
4096
Figure 19. AD9716 Precalibration DNL at 3.3 V
0.13 0.13
Figure 22. AD9716 Postcalibration DNL at 3.3 V
POSTCALIBRATION INL (LSB)
0 128 256 384 512 CODE 640 768 896 1024
07265-018
PRECALIBRATION INL (LSB)
0.08
0.08
0.03
0.03
-0.02
-0.02
-0.07
-0.07
-0.12
-0.12
0
128
256
384
512 CODE
640
768
896
1024
Figure 20. AD9715 Precalibration INL at 1.8 V
Figure 23. AD9715 Postcalibration INL at 1.8 V
Rev. 0 | Page 19 of 48
AD9714/AD9715/AD9716/AD9717
0.13 0.13
POSTCALIBRATION DNL (LSB)
07265-022
0.08
0.08
PRECALIBRATION DNL (LSB)
0.03
0.03
-0.02
-0.02
-0.07
-0.07
0
128
256
384
512 CODE
640
768
896
1024
0
128
256
384
512 CODE
640
768
896
1024
Figure 24. AD9715 Precalibration DNL at 1.8 V
0.13 0.13
Figure 27. AD9715 Postcalibration DNL at 1.8 V
0.08
0.08
POSTCALIBRATION INL (LSB)
PRECALIBRATION INL (LSB)
0.03
0.03
-0.02
-0.02
-0.07
-0.07
07265-023
0
128
256
384
512 CODE
640
768
896
1024
0
128
256
384
512 CODE
640
768
896
1024
Figure 25. AD9715 Precalibration INL at 3.3 V
0.13 0.13
Figure 28. AD9715 Postcalibration INL at 3.3 V
0.08
0.08
0.03
POSTCALIBRATION DNL (LSB)
PRECALIBRATION DNL (LSB)
0.03
-0.02
-0.02
-0.07
-0.07
07265-024
0
128
256
384
512 CODE
640
768
896
1024
0
128
256
384
512 CODE
640
768
896
1024
Figure 26. AD9715 Precalibration DNL at 3.3 V
Figure 29. AD9715 Postcalibration DNL at 3.3 V
Rev. 0 | Page 20 of 48
07265-027
-0.12
-0.12
07265-026
-0.12
-0.12
07265-025
-0.12
-0.12
AD9714/AD9715/AD9716/AD9717
0.025 0.020 0.025 0.020
0.010 0.005 0 -0.005 -0.010 -0.015 -0.020
07265-028
POSTCALIBRATION INL (LSB)
PRECALIBRATION INL (LSB)
0.015
0.015 0.010 0.005 0 -0.005 -0.010 -0.015 -0.020
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE
Figure 30. AD9714 Precalibration INL at 1.8 V
0.025 0.020 0.025 0.020
Figure 33. AD9714 Postcalibration INL at 1.8 V
0.010 0.005 0 -0.005 -0.010 -0.015 -0.020
07265-029
POSTCALIBRATION DNL (LSB)
PRECALIBRATION DNL (LSB)
0.015
0.015 0.010 0.005 0 -0.005 -0.010 -0.015 -0.020
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE
Figure 31. AD9714 Precalibration DNL at 1.8 V
0.025 0.020 0.025 0.020
Figure 34. AD9714 Postcalibration DNL at 1.8 V
0.010 0.005 0 -0.005 -0.010 -0.015 -0.020
07265-030
POSTCALIBRATION INL (LSB)
PRECALIBRATION INL (LSB)
0.015
0.015 0.010 0.005 0 -0.005 -0.010 -0.015 -0.020
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE
Figure 32. AD9714 Precalibration INL at 3.3 V
Figure 35. AD9714 Postcalibration INL at 3.3 V
Rev. 0 | Page 21 of 48
07265-033
-0.025
-0.025
07265-032
-0.025
-0.025
07265-031
-0.025
-0.025
AD9714/AD9715/AD9716/AD9717
0.025 0.020
0.025 0.020
0.010 0.005 0 -0.005 -0.010 -0.015 -0.020 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE
07265-034
POSTCALIBRATION DNL (LSB)
PRECALIBRATION DNL (LSB)
0.015
0.015 0.010 0.005 0 -0.005 -0.010 -0.015 -0.020 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE
07265-037
-0.025
-0.025
Figure 36. AD9714 Precalibration DNL at 3.3 V
-126 -129 -132 -135 AD9714 -132 -126
Figure 39. AD9714 Postcalibration DNL at 3.3 V
AD9714
NSD (dBc)
AD9715
NSD (dBc)
-138 -141 -144 -147 -150 -153 -156 0 5 10 15
-138
AD9715
-144 AD9716 AD9717 -150
AD9716 AD9717
07265-035
20
30 35 fOUT (MHz)
25
40
45
50
55
0
5
10
15
20
25
30
35
40
45
50
55
fOUT (MHz)
Figure 37. Noise Spectral Density at 3.3 V
Figure 40. AD9714/AD9715/AD9716/AD9717 Noise Spectral Density at 1.8 V
93 90
86 AD9715 80
87 AD9715 84 74
SFDR (dBc)
81 AD9716 78 75 72 69
07265-036
SFDR (dBc)
68
AD9714
AD9717 AD9714
62
56 AD9716 0 5 10 15 20 25 30 35 fOUT (MHz) 40 45 50 55 60 50 0 5 10 15 20 25 30 35 fOUT (MHz) 40 AD9717 45 50 55 60
07265-039
66
Figure 38. AD9714/AD9715/AD9716/AD9717 SFDR at 3.3 V
Figure 41. AD9714/AD9715/AD9716/AD9717 SFDR at 1.8 V
Rev. 0 | Page 22 of 48
07265-038
-156
AD9714/AD9715/AD9716/AD9717
100 AD9717 94 AD9716 -64 -61 1mA
IMD (dBc)
88
ACLR (dBc)
AD9715
2mA -67
82
-70 76 AD9714
5
10
15
20
30 fOUT (MHz)
25
35
40
45
50
07265-040
70
20
25
30
35
40
45
fOUT (MHz)
Figure 42. AD9714/AD9715/AD9716/AD9717 IMD at 3.3 V
Figure 45. 1 Carrier ACLR First Adjacent Channel at 1.8 V
88
-60
82
-63 1mA
76
-66
IMD (dBc)
ACLR (dBc)
70 AD9714 AD9715 AD9716 AD9717
-69 2mA -72 4mA
64
58
-75
5
10
15
20
30 fOUT (MHz)
25
35
40
45
50
07265-098
52
20
25
30
35
40
45
fOUT (MHz)
Figure 43. AD9714/AD9715/AD9716/AD9717 IMD at 1.8 V
Figure 46. 1 Carrier ACLR First Adjacent Channel at 3.3 V
25 30 20 TOTAL CURRENT @ 2mA OUT
3.3V CURRENT (mA)
TOTAL CURRENT @ 1mA OUT TOTAL CURRENT @ 2mA OUT TOTAL CURRENT @ 4mA OUT
CURRENT (mA)
15 TOTAL CURRENT @ 1mA OUT 10 AVDD @ 2mA OUT AVDD @ 1mA OUT 5 DVDD CVDD
07265-041
20 AVDD @ 4mA OUT AVDD @ 2mA OUT 10 AVDD @ 1mA OUT DVDD CVDD 0
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
fOUT (MHz)
fOUT (MHz)
Figure 44. Supply Current vs. Frequency at 1.8 V
Figure 47. Supply Current vs. Frequency at 3.3 V
Rev. 0 | Page 23 of 48
07265-044
0
07265-097
-78 15
07265-099
-73 15
AD9714/AD9715/AD9716/AD9717
-60 1mA PRECAL -60 1mA PRECAL
-65 2mA POSTCAL
ACLR (dBc) ACLR (dBc)
-65 1mA POSTCAL
1mA POSTCAL -70 2mA PRECAL 4mA POSTCAL -75
2mA POSTCAL
-70
2mA PRECAL 4mA PRECAL
07265-070
25
35
45
fOUT (MHz)
30
40
fOUT (MHz)
Figure 48. AD9717 1-Carrier W-CDMA First Adjacent Channel ACLR 3.3 V
Figure 51. AD9717 1-Carrier W-CDMA Third Adjacent Channel ACLR 1.8 V
-60 1mA PRECAL
-55
1mA PRECAL 1mA POSTCAL
1mA POSTCAL -65
ACLR (dBc) ACLR (dBc)
-60
2mA PRECAL
2mA POSTCAL -70
-65
2mA POSTCAL
2mA PRECAL
07265-068 07265-073 07265-074
-75 15
25
35
45
-70 15
20
25
30
35
40
fOUT (MHz)
fOUT (MHz)
Figure 49. AD9717 1-Carrier W-CDMA First Adjacent Channel ACLR 1.8 V
-60 1mA PRECAL
Figure 52. AD9717 1-Carrier W-CDMA First Adjacent Channel ACLR 1.8 V
-60 1mA PRECAL
-65
-65
ACLR (dBc) ACLR (dBc)
2mA PRECAL 1mA POSTCAL -70
1mA POSTCAL 2mA PRECAL -70
-75
4mA PRECAL
2mA POSTCAL
2mA POSTCAL
07265-071
4mA POSTCAL
-75 15
25
35
45
-80 15
25
35
45
fOUT (MHz)
fOUT (MHz)
Figure 50. AD9717 1-Carrier W-CDMA Second Adjacent Channel ACLR 1.8 V
Figure 53. AD9717 1-Carrier W-CDMA Second Adjacent Channel ACLR 3.3 V
Rev. 0 | Page 24 of 48
07265-072
-80 15
-75 20
AD9714/AD9715/AD9716/AD9717
-60 1mA PRECAL 1mA PRECAL -65 -60
ACLR (dBc)
-55
2mA PRECAL
ACLR (dBc)
1mA POSTCAL -70 4mA PRECAL -75
1mA POSTCAL
2mA PRECAL
2mA POSTCAL
-65 2mA POSTCAL
4mA POSTCAL
07265-075
30
40
25
30
35
40
fOUT (MHz)
fOUT (MHz)
Figure 54. AD9717 1-Carrier W-CDMA Third Adjacent Channel ACLR 3.3 V
Figure 57. AD9717 2-Carrier W-CDMA Third Adjacent Channel ACLR 1.8 V
-55 1mA PRECAL -60 2mA PRECAL
ACLR (dBc)
1mA POSTCAL
-65 2mA POSTCAL
4mA PRECAL -70
07265-076
-75 15
20
25
30
35
40
CENTER 22.90MHz
fOUT (MHz)
VBW 300kHz
SPAN 38.84MHz
Figure 55. AD9717 1-Carrier W-CDMA First Adjacent Channel ACLR 3.3 V
Figure 58. AD9717 ACLR 1-Carrier 1.8 V
-55 1mA PRECAL
-55 1mA PRECAL
-60 -60
ACLR (dBc)
1mA POSTCAL 1mA POSTCAL 2mA PRECAL
ACLR (dBc)
2mA PRECAL
-65
-65 -70 2mA POSTCAL 4mA PRECAL
07265-077
2mA POSTCAL
4mA POSTCAL 30 35 40
07265-080
-70 15
20
25
30
35
40
-75 15
20
25
fOUT (MHz)
fOUT (MHz)
Figure 56. AD9717 2-Carrier W-CDMA Second Adjacent Channel ACLR 1.8 V
Figure 59. AD9717 2-Carrier W-CDMA Second Adjacent Channel ACLR 3.3 V
Rev. 0 | Page 25 of 48
07265-079
4mA POSTCAL
10dB/DIV
07265-078
-80 20
-70 20
AD9714/AD9715/AD9716/AD9717
-55 1mA PRECAL
-10 -20
-60 1mA POSTCAL 2mA PRECAL -65
-30 -40 -50
ACLR (dBc)
(dBm)
2mA POSTCAL 4mA PRECAL 4mA POSTCAL
07265-081
-60 -70 -80 -90
-70
25
30 fOUT (MHz)
35
40
-110
START 1MHz
1.5MHz/DIV
STOP 16MHz
Figure 60. AD9717 2-Carrier W-CDMA Third Adjacent Channel ACLR 3.3 V
Figure 63. AD9717 Single Tone 1.8 V
-10 -20 -30 -40
10dB/DIV
-50
(dBm)
-60 -70 -80 -90
-100
07265-082
CENTER 22.90MHz
VBW 300kHz
SPAN 38.84MHz
-110
START 1MHz
1.5MHz/DIV
STOP 16MHz
Figure 61. AD9717 ACLR 1-Carrier 3.3 V
Figure 64. AD9717 Two Tone 1.8 V
10dB/DIV
10dB/DIV
07265-083
CENTER 22.90MHz
VBW 300kHz
SPAN 38.84MHz
CENTER 22.90MHz
VBW 300kHz
SPAN 38.84MHz
Figure 62.AD9717 ACLR 2-Carrier 1.8 V
Figure 65. AD9717 ACLR 2-Carrier 3.3 V
Rev. 0 | Page 26 of 48
07265-086
07265-085
07265-084
-75 20
-100
AD9714/AD9715/AD9716/AD9717
91
-10 -20 -30 -40 -50
(dBm)
IMD (dBc)
85 88 0dB
-3dB
-60 -70 -80 -90
82
-6dB
79
-100
07265-087
-110
5
10
15
20
25
30
35
40
45
50
START 1MHz
1.4MHz/DIV
STOP 15MHz
fIN (MHz)
Figure 66. AD9717 Single Tone, 3.3 V
-10 -20 -30
80 90 85
Figure 69. IMD vs. Digital Input Level 3.3 V
-40
SFDR (dBc)
-6dB 75 70 65 60 -3dB 0dB
-50
(dBm)
-60 -70 -80 -90
-100
07265-088
55
07265-091 07265-092
-110
50
START 1MHz
1.4MHz/DIV
STOP 15MHz
0
10
20
30
40
50
60
fIN (MHz)
Figure 67. AD9717 Two Tone, 3.3 V
88 90 85 80 76 -3dB -6dB 75 70 65 60 58 55
07265-089
Figure 70. SFDR vs. Digital Input Level 3.3 V
82
-6dB
70
SFDR (dBc)
IMD (dBc)
0dB
-3dB
64
0dB
52
5
10
15
20
25 30 FIN (MHz)
35
40
45
50
50
0
10
20
30
40
50
60
fIN (MHz)
Figure 68. IMD vs. Digital Input Level 1.8 V
Figure 71. SFDR vs. Digital Input Level 1.8 V
Rev. 0 | Page 27 of 48
07265-090
76
AD9714/AD9715/AD9716/AD9717
108 102 96 90 +85C +25C -40C 90 4mA 85 80 75 70 65 60 1mA 55
07265-100
07265-096 07265-069
SFDR (dBc)
84 78 72 66 60 54
SFDR (dBc)
2mA
0
5
10
15
20
25
30 35 fOUT (MHz)
40
45
50
55
60
50
0
10
20
30
40
50
60
fOUT (MHz)
Figure 72. SFDR Over Temperature at 3.3 V
Figure 74. SFDR vs. fOUT
90
1.0 0.8 0.6 INL
85
IMD (dBc)
4mA 75 1mA 70
INL, DNL (LSB)
80
0.4 0.2 0 DNL
65
-0.2 -0.4
5
10
15
20
25
30
35
40
45
50
07265-094
60
0
128
256
384
fOUT (MHz)
512 CODE
640
768
896
1024
Figure 73. IMD vs. fOUT, FCLK = 125 MHz
Figure 75. AUXDAC DNL and INL
Rev. 0 | Page 28 of 48
AD9714/AD9715/AD9716/AD9717 TERMINOLOGY
Linearity Error or Integral Nonlinearity (INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error Offset error is the deviation of the output current from the ideal of zero. For IOUTP, 0 mA output is expected when the inputs are all 0. For IOUTN, 0 mA output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range Output compliant range is the range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient value (25C) to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of fullscale range per degree Celsius (ppm FSR/C). For reference drift, the drift is reported in parts per million per degree Celsius (ppm/C). Power Supply Rejection Power supply rejection is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Spurious Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in dBc between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.
Rev. 0 | Page 29 of 48
AD9714/AD9715/AD9716/AD9717 THEORY OF OPERATION
CS/PWRDN
FSADJQ/AUXQ SDIO/FORMAT RESET/PINMD SCLK/CLKMD FSADJI/AUXI DB13 (MSB) REFIO DB12 CMLI
1V DB11 DB10 DB9 DB8 DVDDIO DVSS DVDD DB7 DB6 DB5 CLOCK DIST 1.8V LDO IREF 100A BAND GAP 1 INTO 2 INTERLEAVED DATA INTERFACE I DATA SPI INTERFACE RSET 16k 10k
AD9714/AD9715/ AD9716/AD9717
RSET 16k RCM 1k TO 250
RLIN 500 IOUTN IOUTP 500 RLIP AVDD AVSS RLQP 500
I DAC
AUX1DAC
AUX2DAC
Q DATA
Q DAC 500
QOUTP QOUTN RLQN
RCM 1k TO 250
DCLKIO
CLKIN
DB0 (LSB)
CMLQ
CVDD
CVSS
DB4
DB3
DB2
DB1
Figure 76. Simplified Block Diagram
Figure 76 shows a simplified block diagram of the AD9714/ AD9715/AD9716/AD9717 that consists of two DACs, digital control logic, and a full-scale output current control. The DAC contains a PMOS current source array capable of providing a nominal full-scale current (IOUTFS) of 2 mA and a maximum of 4 mA. The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16 of an MSB current source. The remaining LSBs are binary weighted fractions of the current sources of the middle bits. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the high output impedance of the DAC (that is, >200 M). All of these current sources are switched to one or the other of the two output nodes (IOUTP or IOUTN) via PMOS differential current switches. The switches are based on the architecture that was pioneered in the AD976x family, with further refinements to reduce distortion contributed by the switching transient. This switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. The analog and digital I/O sections of the AD9714/AD9715/ AD9716/AD9717 have separate power supply inputs (AVDD and DVDDIO) that can operate independently over a 1.7 V to 3.5 V
range. The core digital section, which is powered optionally by either the on-chip LDO or through DVDD (Pin 7), is capable of operating at a rate of up to 125 MSPS. It consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.0 V band gap voltage reference, and a reference control amplifier. Each DAC full-scale output current is regulated by the reference control amplifier and can be set from 1 mA to 4 mA via an external resistor, RSET, connected to its full-scale adjust pin (FSADJ). The external resistor, in combination with both the reference control amplifier and voltage reference, VREFIO, sets the reference current, IREF, which is replicated to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is 32 x IREF. Optional on-chip RSET resistors are provided that can be programmed between a nominal value of 8 k to 32 k (4 mA to 1 mA IOUTFS ). The AD9714/AD9715/AD9716/AD9717 provide the option of setting the output common mode to a value other than ACOM via the output common-mode pins (CMLI and CMLQ). This facilitates directly interfacing the output of the AD9714/AD9715/ AD9716/AD9717 to components that require common-mode levels greater than 0 V.
Rev. 0 | Page 30 of 48
07265-046
AD9714/AD9715/AD9716/AD9717 SERIAL PERIPHERAL INTERFACE (SPI)
The serial port of the AD9714/AD9715/AD9716/AD9717 is a flexible, synchronous serial communications port allowing easy interfacing to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI(R) and Intel(R) SSR protocols. The interface allows read/write access to all registers that configure the AD9714/AD9715/AD9716/AD9717. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The serial interface port of the AD9714/ AD9715/AD9716/AD9717 is configured as a single I/O pin on the SDIO pin.
INSTRUCTION BYTE
The instruction byte contains the information shown in Table 11. Table 11.
MSB DB7 R/W DB6 N1 DB5 N0 DB4 A4 DB3 A3 DB2 A2 DB1 A1 LSB DB0 A0
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communications cycle on the AD9714/ AD9715/AD9716/AD9717. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9714/AD9715/ AD9716/AD9717, coinciding with the first eight SCLK rising edges. In Phase 2, the instruction byte provides the serial port controller of the AD9714/AD9715/AD9716/AD9717 with information regarding the data transfer cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9714/AD9715/AD9716/AD9717. A Logic 1 on Pin 35 (RESET/PINMD), followed by a Logic 0, resets the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the SPI port. If the SPI port is in the midst of an instruction cycle or a data transfer cycle, none of the present data is written. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9714/ AD9715/AD9716/AD9717 and the system controller. Phase 2 of the communication cycle is a transfer of one, two, three, or four data bytes, as determined by the instruction byte. Using one multibyte transfer is the preferred method. Single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte.
R/W (Bit 7 of the instruction byte) determines whether a read or a write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation. Logic 0 indicates a write operation. N1 and N0 (Bit 6 and Bit 5 of the instruction byte) determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in Table 12. Table 12. Byte Transfer Count
N1 0 0 1 1 N0 0 1 0 1 Description Transfer 1 byte Transfer 2 bytes Transfer 3 bytes Transfer 4 bytes
A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the instruction byte) determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The following register addresses are generated internally, based on the LSBFIRST bit (Register 0x00, Bit 6).
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK--Serial Clock
The serial clock pin is used to synchronize data to and from the AD9714/AD9715/AD9716/AD9717 and to run the internal state machines. The SCLK maximum frequency is 20 MHz. All data input to the AD9714/AD9715/AD9716/AD9717 is registered on the rising edge of SCLK. All data is driven out of the AD9714/ AD9715/AD9716/AD9717 on the falling edge of SCLK.
CS--Chip Select
An active low input starts and gates a communications cycle. It allows more than one device to be used on the same serial communications lines. The SDIO/FORMAT pin reaches a high impedance state when this input is high. Chip select should stay low during the entire communications cycle.
SDIO--Serial Data I/O
The SDIO pin is used as a bidirectional data line to transmit and receive data.
Rev. 0 | Page 31 of 48
AD9714/AD9715/AD9716/AD9717
MSB/LSB TRANSFERS
The serial port of the AD9714/AD9715/AD9716/AD9717 can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the LSBFIRST bit (Register 0x00, Bit 6). The default is MSB first (LSBFIRST = 0). When LSBFIRST = 0 (MSB first), the instruction and data bytes must be written from the most significant bit to the least significant bit. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow in order from a high address to a low address. In MSB first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communications cycle. When LSBFIRST = 1 (LSB first), the instruction and data bytes must be written from the least significant bit to the most significant bit. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle. The serial port controller data address of the AD9714/AD9715/ AD9716/AD9717 decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB first mode is active. The serial port controller address increments from the data address written toward 0x1F for multibyte I/O operations if the LSB first mode is active.
SERIAL PORT OPERATION
The serial port configuration of the AD9714/AD9715/AD9716/ AD9717 is controlled by Register 0x00. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register can occur during the middle of the communications cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communications cycle. The same considerations apply to setting the software reset, RESET (Register 0x00, Bit 5). All registers are set to their default values except Register 0x00, which remains unchanged. Use of single-byte transfers or initiating a software reset is recommended when changing serial port configurations to prevent unexpected device behavior.
PIN MODE
The AD9714/AD9715/AD9716/AD9717 can also be operated without ever writing to the serial port. With RESET/PINMD pin tied high, the SCLK pin becomes CLKMD to provide for clock mode control (see the Retimer section), the former SDIO pin selects the input data format, and the CS pin serves to power down the device. Operation is otherwise exactly as defined by the default register values in Table 12, therefore external resistors at FSADJI and FSADJQ are needed to set the DAC currents, and both DACs are active. This is also a convenient quick checkout mode. DAC currents can be externally adjusted in pin mode by sourcing or sinking currents at the FSADJI/AUXI and FSADJQ/AUXQ pins as desired with the fixed resistors installed. An op amp output with appropriate series resistance would be one of many possibilities. This has the same effect as changing the resistor value. Place at least 10 k resistors in series right at the DAC to guard against accidental short circuits and noise modulation. The REFIO pin can be adjusted 25% in a similar manner, if desired.
Rev. 0 | Page 32 of 48
AD9714/AD9715/AD9716/AD9717 SPI REGISTER MAP
Table 13.
Name SPI Control Power Down Data Control I DAC Gain IRSET IRCML Q DAC Gain QRSET QRCML AUXDAC Q AUX CTLQ AUXDAC I AUX CTLI Reference Resistor Cal Control Cal Memory Memory Address Memory Data Memory R/W CLKMODE Version Addr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x14 0x1F Default 0x00 0x40 0x34 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x34 0x00 0x00 N/A Bit 7 LDOOFF TWOS IRSETEN IRCMLEN QRSETEN QRCMLEN QAUXEN IAUXEN QAUXRNG[1:0] IAUXRNG[1:0] Bit 6 LSBFIRST LDOSTAT Bit 5 RESET PWRDN IFIRST Bit 4 LNGINS Q DACOFF IRISING Bit 3 Bit 2 Bit 1 ICLKOFF DCOSGL Bit 0 EXTREF DCODBL
I DACOFF QCLKOFF SIMULBIT DCI_EN I DACGAIN[5:0] IRSET[5:0] IRCML[5:0] Q DACGAIN[5:0] QRSET[5:0] QRCML[5:0] QAUXDAC[7:0] QAUXOFS[2:0] IAUXDAC[7:0] IAUXOFS[2:0] RREF[5:0]
QAUXDAC[9:8] IAUXDAC[9:8]
PRELDQ CALSTATQ
PRELDI CALSTATI
CALSELQ
CALSELI
CALRSTQ CALRSTI CLKMODEQ[1:0]
CALCLK DIVSEL[2:0] CALMEMQ[1:0] MEMADDR[5:0] MEMDATA[5:0] CALEN SMEMWR SMEMRD SEARCHING REACQUIRE CLKMODEN VERSION[7:0]
CALMEMI[1:0]
UNCALQ UNCALI CLKMODEI[1:0]
Rev. 0 | Page 33 of 48
AD9714/AD9715/AD9716/AD9717 SPI REGISTER DESCRIPTIONS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Table 14.
Register SPI Control Address 0x00 Bit 6 Name LSBFIRST Function 0: MSB first, per SPI standard 1: LSB first, per SPI standard Note that the user must always change the LSB/MSB order in single-byte instructions to avoid erratic behavior due to bit order errors Execute software reset of SPI and controllers, reload default register values except Register 0x00 1: Set software reset; write 0 on the next (or any following) cycle to release the reset 0: The SPI instruction word utilizes a 5-bit address 1: The SPI instruction word utilizes a 13-bit address 1: turn core LDO voltage regulator off 0: Indicates core LDO voltage regulator is off 1: Indicates core LDO voltage regulator is on 1: Powers down all analog and digital circuitry except for SPI logic 1: Turns off Q DAC output current 1: Turns off I DAC output current 1: Turns off Q DAC clock 1: Turns off I DAC clock 1: Powers down internal voltage reference (external reference required) 0: Unsigned binary input data format 1: Twos complement input data format 0: Pairing of data--Q first of pair on data input pads 1: Pairing of data--I first of pair on data input pads (default) 0: Q data latched on DCLKIO rising edge 1: I data latched on DCLKIO falling edge (default) 0: Allows simultaneous input and output enable on DCLKIO 1: Disallows simultaneous input and output enable on DCLKIO Controls the use of DCLKIO pad for data clock input 0: Data clock input disabled 1: Data clock input enabled (default) Controls the use of DCLKIO pad for data clock output 0: Data clock output disabled 1: Data clock output enabled; regular strength driver Controls the use of DCLKIO pad for data clock output 0: DCOBL data clock output disabled 1: DCOBL data clock output enabled; paralleled with DCOSGL for 2x drive current DAC I fine gain adjustment; alters the full-scale current as shown in Figure 86 1: Enables the on-chip RSET value to be changed Changes the value of the on-chip RSET resistor; this scales the full-scale current of the DAC in ~0.25 dB steps (nonlinear); see Figure 85 000000: RSET = 8 k 100000: RSET = 16 k 111111: RSET = 32 k
5
RESET
4 Power Down
0x01
LNGINS LDOOFF LDOSTAT PWRDN Q DACOFF I DACOFF QCLKOFF ICLKOFF EXTREF TWOS IFIRST IRISING SIMULBIT DCI_EN
7 6 5 4 3 2 1 0 7 5 4 3 2
Data Control
0x02
1
DCOSGL
0
DCODBL
I DAC Gain IRSET
0x03 0x04
5:0 7 5:0
I DACGAIN[5:0] IRSETEN IRSET[5:0]
Rev. 0 | Page 34 of 48
AD9714/AD9715/AD9716/AD9717
Register IRCML Address 0x05 Bit 7 5:0 Name IRCMLEN IRCML[5:0] Function 1: Enables on-chip RCML adjustment Changes the value of the on-chip RCML resistor; this adjusts the common-mode level of the DAC output stage 000000: RSET = 250 100000: RSET = 625 111111: RSET = 1 k DAC Q fine gain adjustment; alters the full-scale current as shown in Figure 86 1: Enables on-chip RCML adjustment Changes the value of the on-chip RSET resistor; this scales the full-scale current of the DAC in ~0.25 dB steps (nonlinear), see Figure 85 000000: RSET = 8 k 100000: RSET = 16 k 111111: RSET = 32 k 1: Enables on-chip RCML adjustment Changes the value of the on-chip RCML resistor; this adjusts the common-mode level of the DAC output stage 000000, RSET = 250 100000, RSET = 625 111111, RSET = 1 k AUXDAC Q output voltage adjustment word LSBs 0x3FF: Sets AUXDAC Q output to full scale 0x200: Sets AUXDAC Q output to midscale 0x000: Sets AUXDAC Q output to bottom of scale 1: enables AUXDAC Q 00: Sets AUXDAC Q output voltage range to 2 V 01: Sets AUXDAC Q output voltage range to 1.5 V 10: Sets AUXDAC Q output voltage range to 1.0 V 11: Sets AUXDAC Q output voltage range to 0.5 V 000: Sets AUXDAC Q top of range to 1.0 V 001: Sets AUXDAC Q top of range to 1.5 V 010: Sets AUXDAC Q top of range to 2.0 V 011: Sets AUXDAC Q top of range to 2.5 V 100: Sets AUXDAC Q top of range to 2.9 V AUXDAC Q output voltage adjustment word MSBs AUXDAC I output voltage adjustment word LSBs 0x3FF: Sets AUXDAC I output to full scale 0x200: Sets AUXDAC I output to midscale 0x000: Sets AUXDAC I output to bottom of scale 1: enables AUXDAC I 00: Sets AUXDAC I output voltage range to 2 V 01: Sets AUXDAC I output voltage range to 1.5 V 10: Sets AUXDAC I output voltage range to 1.0 V 11: Sets AUXDAC I output voltage range to 0.5 V 000: Sets AUXDAC I top of range to 1.0 V 001: Sets AUXDAC I top of range to 1.5 V 010: Sets AUXDAC I top of range to 2.0 V 011: Sets AUXDAC I top of range to 2.5 V 100: Sets AUXDAC I top of range to 2.9 V AUXDAC I output voltage adjustment word MSBs Permits an adjustment of the on-chip reference voltage and output at REFIO (see Figure 84) 000000: Sets the value of RREF to 8 k, VREF = 0.8 V 100000: Sets the value of RREF to 10 k, VREF = 1.0 V 111111: Sets the value of RREF to 12 k, VREF = 1.2 V
Q DAC Gain QRSET
0x06 0x07
5:0 7 5:0
Q DACGAIN[5:0] QRSETEN QRSET[5:0]
QRCML
0x08
7 5:0
QRCMLEN QRCML[5:0]
AUXDAC Q
0x09
7:0
QAUXDAC[7:0]
AUX CTLQ
0x0A
7 6:5
QAUXEN QAUXRNG[1:0]
4:2
QAUXOFS[2:0]
AUXDAC I
0x0B
1:0 7:0
QAUXDAC[9:8] IAUXDAC[7:0]
AUX CTLI
0x0C
7 6:5
IAUXEN IAUXRNG[1:0]
4:2
IAUXOFS[2:0]
Reference Resistor
0x0D
1:0 5:0
IAUXDAC[9:8] RREF[5:0]
Rev. 0 | Page 35 of 48
AD9714/AD9715/AD9716/AD9717
Register Cal Control Address 0x0E Bit 7 6 5 4 3 2:0 Cal Memory 0x0F 7 6 3:2 Name PRELDQ PRELDI CALSELQ CALSELI CALCLK DIVSEL[2:0] CALSTATQ CALSTATI CALMEMQ[1:0] Function 0: Preload Q DAC calibration reference set to 32 1: Preload Q DAC calibration reference set by user (Cal Address 1) 0: Preload I DAC calibration reference set to 32 1: Preload I DAC calibration reference set by user (Cal Address 1) 1: Select Q DAC self-calibration 1: Select I DAC self-calibration 1: Calibration clock enabled Calibration clock divide ratio from DAC clock rate 000 = divide by 256; 001 = divide by 128 ... 110 = divide by 4; 111 = divide by 2 1: Calibration of Q DAC complete 1: Calibration of I DAC complete Status of Q DAC calibration memory 00: Uncalibrated 01: Self-calibrated 10: User calibrated Status of I DAC calibration memory 00: Uncalibrated 01: Self-calibrated 10: User calibrated Address of static memory to be accessed Data for static memory access 1: Clear CALSTATQ 1: Clear CALSTATI 1: Initiate device self-calibration 1: Write to static memory (calibration coefficients) 1: Read from static memory (calibration coefficients) 1: Reset Q DAC calibration coefficients to default (uncalibrated) 1: Reset I DAC calibration coefficients to default (uncalibrated) Q datapath retimer clock select output (that is, readback after Q retimer acquires) High indicates internal data path retimer is searching for clock relationship (device output is not usable while this bit is high) Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship 0: CLKMODEI/Q values computed by the two retimers and read back in CLKMODEI[1:0] and CLKMODEQ[1:0] 1: CLKMODE values set in CLKMODEI[1:0] over-ride both I and Q retimers 0: CLKMODEN, read only; clock phase chosen by retimer 1: CLKMODEN, read/write; value in this register sets I and Q clock phases Hardware version of the device
1:0
CALMEMI[1:0]
Memory Address Memory Data Memory R/W
0x10 0x11 0x12
5:0 5:0 7 6 4 3 2 1 0 7:6 4 3 2
MEMADDR[5:0] MEMDATA[5:0] CALRSTQ CALRSTI CALEN SMEMWR SMEMRD UNCALQ UNCALI CLKMODEQ[1:0] SEARCHING REACQUIRE CLKMODEN
CLKMODE
0x14
1:0 Version 0x1F 7:0
CLKMODEI[1:0] VERSION[7:0]
Rev. 0 | Page 36 of 48
AD9714/AD9715/AD9716/AD9717 DIGITAL INTERFACE OPERATION
Digital data for the I and Q DACs is supplied over a single parallel bus (DB[MSB:0]) accompanied by a qualifying clock (DCLKIO). The I and Q data is provided to the chip in an interleaved double data rate (DDR) format. The maximum guaranteed data rate is 250 MSPS with a 125 MHz clock. The order of data pairing and the sampling edge selection is user programmable using the IFIRST and IRISING configuration bits, resulting in four possible timing diagrams. These are shown in Figure 77, Figure 78, Figure 79, and Figure 80.
DCLKIO DCLKIO DB[13:0] Z A B C D E F G H DB[13:0] I DATA Z B D F I DATA Y A C E Z A B C D E F G H DCLKIO DB[13:0] Z A B C D E F G H
I DATA
Z
B
D
F
Q DATA
A
C
E
G
Figure 79. Timing Diagram with IFIRST = 1, IRISING = 0
Q DATA
Y
A
C
E
07265-047
Figure 77. Timing Diagram with IFIRST = 0, IRISING = 0
Q DATA
Z
B
D
F
Figure 80. Timing Diagram with IFIRST = 1, IRISING = 1
DCLKIO
DB[13:0]
Z
A
B
C
D
E
F
G
H
Ideally, the rising and falling edges of the clock fall in the center of the keep-in-window formed by the set-up and hold times, tS and tH. A detailed timing diagram is shown in Figure 81.
E
I DATA
Y
A
C
DCLKIO
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Q DATA
X
Z
B
D
tS tH
DB[13:0]
tS tH
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Figure 78. Timing Diagram with IFIRST = 0, IRISING = 1
Figure 81. Set-Up and Hold Times for All Input Modes
In addition to the different timing modes listed in Table 2, the input data can also be presented to the device in either unsigned binary or twos complement format. The format type is chosen via the TWOS configuration bit.
Rev. 0 | Page 37 of 48
07265-050
07265-049
AD9714/AD9715/AD9716/AD9717
OR D-FF DATA DB[13:0] (INPUT) 0 D-FF 1 D-FF 2 RETIMER-CLK D-FF 3 TO DAC CORE D-FF 4 IOUT
DCLKIO-INT
DCLKIO-INT
RETIMER-CLK
IOUT NOTES D-FFs: 0: RISING OR FALLING EDGE TRIGGERED FOR I OR Q DATA. 1, 2, 3, 4: RISING EDGE TRIGGERED.
DELAY1
IE
IE DELAY2
DELAY1
OE
DCLKIO (INPUT/OUTPUT)
CLKIN (INPUT)
Figure 82. Simplified Diagram of AD9714/AD9715/AD9716/AD9717 Timing
DIGITAL DATA LATCHING AND RETIMER SECTION
The AD9714/AD9715/AD9716/AD9717 have two clock inputs, DCLKIO and CLKIN. The CLKIN is the analog clock whose jitter affects DAC performance and the DCLKIO is a digital clock, probably from an FPGA that needs to have a fixed relationship with the input data to ensure that the data is picked up correctly by the flip-flops on the pads. Figure 82 is a simplified diagram of the entire data capture system in the AD9714/AD9715/AD9716/AD9717. The double data rate input data, DB[13:0], is latched at the pads/pins either on the rising edge or the falling edge of the DCLKIO-INT clock, as determined by IRISING, the SPI bit. IFIRST, the SPI bit determines which channel data is latched first (that is, I or Q). The captured data is then retimed to the internal clock (CLKIN-INT) in the retimer block before being sent to the final analog DAC core (D-FF (4)), which controls the current steering output switches. All delay blocks depicted in Figure 82 are noninverting, and any wires without an explicit delay block can be assumed to have no delay for the purpose of understanding. Only one channel is shown in Figure 82 with the data pads (DB[13:0]) serving as double data rate pads for both channels. The default PINMD and SPI settings are IE = high (closed) and OE = low (open). These settings are enabled when RESET/ PINMD (Pin 35) is held high. In this mode, the user has to supply both DCLKIO and CLKIN. In PINMD, it is also recommended that the DCLKIO and the CLKIN be in-phase for proper functioning of the DAC, which can easily be ensured by tying the pins together on the PCB. If the user can access the SPI, settling IE low (that is, IE is high) causes the CLKIN to be used as the DCLKIO also.
Settling OE high in the SPI allows the user to get a DCLKIO output from the CLKIN input for use in the user's PCB system. It is strongly recommended that IE = OE = high not be used even though the device may appear to function correctly.
Retimer
The AD9714/AD9715/AD9716/AD9717 have an internal data retimer circuit that compares the CLKIN-INT and DCLKIO-INT clocks and, depending on their phase relationship, selects a retimer clock (RETIMER-CLK) to safely transfer data from the DCLKIO used at the chip's input interface to the CLKIN used to clock the analog DAC cores (D-FF (4)). The retimer selects one of the three phases shown in Figure 83. The retimer is controlled by the SPI bits is shown in Table 15.
1/2 PERIOD DATA CLOCK RETIMER-CLKs 180 90 270 1/4 PERIOD 1/2 PERIOD
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Figure 83. RETIMER-CLK Phases
Note that in most cases, more than one retimer phase works, and in such cases, the retimer arbitrarily picks one phase that works. The retimer cannot pick the best or safest phase. If the user has a working knowledge of the exact phase relationship between DCLKIO and CLKIN (and thus DCLKIO-INT and CLKIN-INT, because the delay is approximately the same for both clocks and equal to DELAY1), then the retimer can be forced to this phase with CLKMODEN = 1 as described in Table 15 and the following paragraphs.
Rev. 0 | Page 38 of 48
07265-052
AD9714/AD9715/AD9716/AD9717
Table 15. Timer Register List
Bit Name CLKMODEQ[1:0] Searching Reacquire CLKMODEN CLKMODEI[1:0] Description Q datapath retimer clock selected output. Valid after SEARCHING goes low. High indicates the internal data path retimer is searching for clock relationship (DAC is not usable until it is low again). Changing this bit from 0 to 1 causes the data path retimer circuit to reacquire the clock relationship. 0: Uses CLKMODEI/CLKMODEQ values (as computed by the two internal retimers) for I and Q clocking. 1: Uses CLKMODE value set in CLKMODEI[1:0] for both I and Q retimers (that is, force the retimer). I datapath retimer clock selected output. Valid after searching goes low. If CLKMODEN = 1, a value written to this register overrides both I and Q automatic retimer values.
Table 16. CLKMODE Details
CLKMODEI[1:0]/CLKMODEQ[1:0] 00 01 10 11 DCLKIO-to-CLKIN Phase Relationship 0 to 90 90 to 180 180 to 270 270 to 360 RETIMER-CLK Selected Phase 2 Phase 3 Phase 3 Phase 1
When reset is pulsed high and then returns low (the part is in SPI mode), the retimer runs and automatically selects a suitable clock phase for the RETIMER-CLK within 128 clock cycles. The SPI searching bit returns to low, indicating that the retimer has locked and the part is ready for use. The reacquire bit can be used to reinitiate phase detection in the I and Q retimers at any time. CLKMODEQ[1:0] and CLKMODEI[1:0] provide readback for the values picked by the internal phase detectors in the retimer (see Table 16). To force the two retimers (I and Q) to pick a particular phase for the retimer clock (they must both be forced to the same value), CLKMODEN should be set high and the required phase value is written into CLKMODEI[1:0] and CLKMODEQ[1:0]. For example, if the DCLKIO and the CLKIN are in phase to first order, the user could safely force the retimers to pick Phase 2 for the RETIMER-CLK. This forcing function may be useful for synchronizing multiple devices. In pin mode, it is expected that the user tie CLKIN and DCLKIO together. The device has a small amount of programmable functionality using the now unused SPI pins (SCLK, SDIO, and CS). If the two chip clocks are tied together, the SCLK pin can be tied to ground and the chip uses a clock for the retimer that is 180 out of phase with the two input clocks (that is, Phase 2, which is the safest or best option). The chip has an additional option in pin mode when the redefined SCLK pin is high. Use this mode if utilizing pin mode, but CLKIN and DCLKIO are not tied together (that is, not in phase). Holding SCLK high
causes the internal clock detector to use the phase detector output to determine which clock to use in the retimer (that is, select a suitable RETIMER-CLK phase). The action of taking SCLK high causes the internal phase detector to reexamine the two clocks and determine the relative phase. Whenever the user wants to reevaluate the relative phase of the two clocks, the SCLK pin can be taken low and then high again.
ESTIMATING THE OVERALL DAC PIPELINE DELAY
DAC pipeline latency is affected by the phase of the RETIMERCLK that is selected. If latency is critical to the system and needs to be constant, the retimer should be forced to a particular phase and not be allowed to automatically select a phase each time. Consider the case when DCLKIO = CLKIN (that is, in phase), and the RETIMER-CLK is forced to Phase 2. Assume that IRISING is 1 (that is, I data is latched on the rising edge and Q data on the falling edge). Then the latency to the output for the I-channel is 3 clock cycles (D-FF (1), D-FF (3), and D-FF (4), but not D-FF (2) because it is latched on the half clock cycle or 180). The latency to the output for the Q-channel from the time the falling edge latches it at the pads in D-FF (0) is 2.5 clock cycles (1/2 clock cycle to D-FF (1), 1 clock cycle to D-FF (3), and 1 clock cycle to D-FF (4)). This latency for the AD9714/AD9715/ AD9716/AD9717 is case specific and needs to be calculated based on the RETIMER-CLK phase that is automatically selected or manually forced.
Rev. 0 | Page 39 of 48
AD9714/AD9715/AD9716/AD9717
SELF-CALIBRATION
The AD9714/AD9715/AD9716/AD9717 have a self-calibration feature that improves the DNL of the device. Performing a selfcalibration on the device improves device performance in low frequency applications. The device performance in applications where the analog output frequencies are above 5 MHz are generally influenced more by dynamic device behavior than by DNL, and in these cases, self-calibration is unlikely to provide much benefit. The calibration clock frequency is equal to the DAC clock divided by the division factor chosen by the DIVSEL value. Each calibration clock cycle is between 32 and 2048 DAC input clock cycles, depending on the value of DIVSEL[2:0] (Register 0x0E, Bits[2:0]). The frequency of the calibration clock should be between 0.5 MHz and 4 MHz for reliable calibrations. Best results are obtained by setting DIVSEL[2:0] (Register 0x0E, Bits[2:0]) to produce a calibration clock frequency between these values. Separate self-calibration hardware is included for each DAC. The DACs can be self-calibrated individually or simultaneously. To perform a device self-calibration, the following procedure can be used: 1. 2. Write 0x00 to Register 0x12. This ensures that the UNCALI and UNCALQ bits are reset. Set up a calibration clock between 0.5 MHz and 4 MHz using DIVSEL[2:0] and then enable the calibration clock by setting the CALCLK bit (Register 0x0E, Bit 3). Select the DAC(s) to self-calibrate by setting either Bit 4 (CALSELI) for the I DAC and/or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. Note that each DAC contains independent calibration hardware so they can be calibrated simultaneously. Start self-calibration by setting Bit 4 in Register 0x12. Wait approximately 300 calibration clock cycles. Check if the self-calibration has completed by reading the CALSTATI bit (Bit 6) and CALSTATQ bit (Bit 7) in Register 0x0F. Logic 1 indicates the calibration has completed. When the self-calibration has completed, write 0x00 to Register 0x12. Disable the calibration clock by clearing the CALCLK bit (Register 0x0E, Bit 3). The AD9714/AD9715/AD9716/AD9717 allow reading and writing of the calibration coefficients. There are 32 coefficients in total. The read/write feature of the coefficients can be useful for improving the results of the self-calibration routine by averaging the results of several self-calibration cycles and loading the averaged results back into the device. To read the calibration coefficients, use the following steps: 1. Select which DAC core to read by setting either Bit 4 (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. Write the address of the first coefficient (0x01) to Register 0x10. Set the SMEMRD bit (Register 0x12, Bit 2 ) by writing 0x04 to Register 0x12. Read the 6-bit value of the first coefficient by reading the contents of Register 0x11. Clear the SMEMRD bit by writing 0x00 to Register 0x12. Repeat Step 2 through Step 4 for each of the remaining 31 coefficients by incrementing the address by one for each read. Deselect the DAC core by clearing either Bit 4 (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E.
2. 3. 4. 5. 6.
To write the calibration coefficients to the device, use the following steps: 1. Select which DAC core to write by setting either Bit 4 (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. Set the SMEMWR bit (Register 0x12, Bit 3) by writing 0x08 to Register 0x12. Write the address of the first coefficient (0x01) to Register 0x10. Write the value of the first coefficient to Register 0x11. Repeat Step 2 through Step 4 for each of the remaining 31 coefficients by incrementing the address by one for each write. Clear the SMEMWR bit by writing 0x00 to Register 0x12. Deselect the DAC core by clearing either Bit 4 (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E.
3.
2. 3. 4. 5.
4. 5.
6. 7.
6. 7.
Rev. 0 | Page 40 of 48
AD9714/AD9715/AD9716/AD9717
COARSE GAIN ADJUSTMENT
Option 1
A coarse full-scale output current adjustment can be achieved using the lower six bits in Register 0x0D. This adds or subtracts up to 20% from the band gap voltage on Pin 34 (REFIO), and the voltage on the FSADJx resistors tracks this change. As a result, the DAC full-scale current varies the same amount. A secondary effect to changing the REFIO voltage is that the full-scale voltage in the AUXDAC also changes by the same magnitude. The register uses twos complement format, in which 011111 maximizes the voltage on the REFIO node and 100000 minimizes the voltage.
1.30 1.25 1.20 1.15 1.10
Option 3
Even when the device is in pin mode, full-scale values can be adjusted by sourcing or sinking current from the FSADJ pins. Any noise injected here appears as amplitude modulation of the output. Thus, a portion of the required series resistance (at least 20 k) must be installed right at the pin. A range of 10% is quite practical using this method.
Option 4
As in Option 3, when the device is in pin mode both full-scale values can be adjusted by sourcing or sinking current from the REFIO pin. Noise injected here appears as amplitude modulation of the output, so a portion of the required series resistance (at least 10 k) must be installed at the pin. A range of 25% is quite practical when using this method.
Fine Gain
Each main DAC has independent fine gain control using the lower six bits in Register 0x03 (I DAC gain) and Register 0x06 (Q DAC gain). Unlike Coarse Gain Option 1, this impacts only the main DAC full-scale output current. This register uses straight binary format. One application where this straight binary format is critical is for side-band suppression while using a quadrature modulator. This is described in more detail in the Applications Information section.
0 8 16 24 32 CODE 40 48 56
07265-054
VREF
1.05 1.00 0.95 0.90 0.85 0.80
2.22 3.3V DAC1 3.3V DAC2 1.8V DAC1 1.8V DAC2
Figure 84. Typical VREF Voltage vs. Code
2.20
Option 2
While utilizing the internal FSADJx resistors, each main DAC can achieve independently controlled coarse gain using the lower six bits of Register 0x04 (IRSET[5:0]) and Register 0x07 (QRSET[5:0]). Unlike Coarse Gain Option 1, this impacts only the main DAC full-scale output current. The register uses twos complement format and allows the output current to be changed in approximately 0.25 dB steps.
4.0 3.5
2.18
FSC (mA)
2.16
2.14
2.12
0
8
16
24 32 40 GAIN DAC CODE
48
56
64
OUTPUT OF I/V CONVERTER (V)
Figure 86. Typical DAC Gain Characteristics
3.0 2.5 2.0 1.5 1.0 0.5
07265-055
VOUT_Q OR VOUT_I
0
0
10
20
30 40 RSET CODE
50
60
Figure 85. Effect of RSET Code
Rev. 0 | Page 41 of 48
07265-056
2.10
AD9714/AD9715/AD9716/AD9717
USING THE INTERNAL TERMINATION RESISTORS
The AD9717/AD9716/AD9715/AD9714 have four 500 termination internal resistors (two for each DAC output). To use these resistors to convert the DAC output current to a voltage, connect each DAC output pin to the adjacent load pin. For example, on the I DAC, IOUTP must be shorted to RLIP and IOUTN must be shorted to RLIN. In addition, the CMLI or CMLQ pin must be connected to ground directly or through a resistor. If the output current is at the nominal 2 mA and the CMLI or CMLQ pin is tied directly to ground, this produces a dc common-mode bias voltage on the DAC output equal to 0.5 V. If the DAC dc bias needs to be higher than 0.5 V, an external resistor can be connected between the CMLI or CMLQ pin and ground. This part also has an internal common-mode resistor that can be enabled. This is explained in the Using the Internal Common-Mode Resistor section.
CML 1200 1100 1000 900
RESISTANCE ()
800 700 600 500 400 300 0 8 16 24 32 CODE 40 48 56
07265-058
200
Figure 88. Typical CML Resistor Value vs. Register Code
Using the CMLx Pins for Optimal Performance
The CMLx pins also serve to change the DAC bias voltages in the parts allowing them to run at higher dc output bias voltages. When running the bias voltage below 0.9 V and an AVDD of 3.3 V, the parts perform optimally when the CMLx pins are tied to ground. When the dc bias increases above 0.9 V, set the CMLx pins at 0.5 V for optimal performance. The maximum dc bias on the DAC output should be kept at or below 1.2 V when the supply is 3.3 V. When the supply is 1.8 V, keep the dc bias close to 0 V and connect the CMLx pins directly to ground.
RCM 500 I DAC OR Q DAC 500
RLIN IOUTN IOUTP RLIP
07265-057
Figure 87. Simplified Internal Load Options
Using the Internal Common-Mode Resistor
These devices contain an adjustable internal common-mode resistor that can be used to increase the dc bias of the DAC outputs. By default, the common-mode resistor is not connected. When enabled, it can be adjusted from ~250 to ~1 k. Each main DAC has an independent adjustment using the lower six bits in Register 0x05 (IRCML[5:0]) and Register 0x08 (QRCML[5:0]).
Rev. 0 | Page 42 of 48
AD9714/AD9715/AD9716/AD9717 APPLICATIONS INFORMATION
OUTPUT CONFIGURATIONS
The following sections illustrate some typical output configurations for the AD9714/AD9715/AD9716/AD9717. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 2 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration can consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application that allows ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, signal gain, and/or a low output impedance. A single-ended output is suitable for applications where low cost and low power consumption are primary concerns. A differential resistor, RDIFF, can be inserted in applications where the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF, as reflected by the transformer, is chosen to provide a source termination that results in a low VSWR. Note that approximately half the signal power is dissipated across RDIFF.
SINGLE-ENDED BUFFERED OUTPUT USING AN OP AMP
An op amp such as the ADA4899-1 can be used to perform a single-ended current-to-voltage conversion, as shown in Figure 90. The AD9714/AD9715/AD9716/AD9717 are configured with a pair of series resistors, RS, off each output. For best distortion performance, RS should be set to 0 . The feedback resistor, RFB, determines the peak-to-peak signal swing by the formula VOUT = RFB x IFS The common-mode voltage of the output is determined by the formula
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-tosingle-ended signal conversion, as shown in Figure 89. The distortion performance of a transformer typically exceeds that available from standard op amps, particularly at higher frequencies. Transformer coupling provides excellent rejection of common-mode distortion (that is, even-order harmonics) over a wide frequency range. It also provides electrical isolation and can deliver voltage gain without adding noise. Transformers with different impedance ratios can also be used for impedance matching purposes. The main disadvantages of transformer coupling are low frequency roll-off, lack-of-power gain, and high output impedance.
IOUTN 29
R VCM = VREF x 1 + FB RB
RFB x I FS - 2
The maximum and minimum voltages out of the amplifier are, respectively,
R VMAX = VREF x 1 + FB RB
VMIN = VMAX - IFS x RFB

CF RB RFB +5V RS
AD9714/AD9715/ AD9716/AD9717
IOUTP 28 OPTIONAL RDIFF
RLOAD
AD9714/AD9715/ AD9716/AD9717
IOUTP 28
-
ADA4899-1 VOUT
07265-059
REFIO 34 RS C
+
-5V
IOUTN 29
Figure 89. Differential Output Using a Transformer
AVSS 25
The center tap on the primary side of the transformer must be connected to a voltage that keeps the voltages on IOUTP and IOUTN within the output common-mode voltage range of the device. Note that the dc component of the DAC output current is equal to IOUTFS and flows out of both IOUTP and IOUTN. The center tap of the transformer should provide a path for this dc current. In most applications, AGND provides the most convenient voltage for the transformer center tap. The complementary voltages appearing at IOUTP and IOUTN (that is, VIOUTP and VIOUTN) swing symmetrically around AGND and should be maintained with the specified output compliance range of the AD9714/AD9715/AD9716/AD9717.
Figure 90. Single-Supply Single-Ended Buffer
Rev. 0 | Page 43 of 48
07265-060
AD9714/AD9715/AD9716/AD9717
DIFFERENTIAL BUFFERED OUTPUT USING AN OP AMP
A dual op amp (see the circuit shown in Figure 91) can be used in a differential version of the single-ended buffer shown in Figure 90. The same R-C network is used to form a one-pole differential, low-pass filter to isolate the op amp inputs from the high frequency images produced by the DAC outputs. The feedback resistors, RFB, determine the differential peak-to-peak signal swing by the formula VOUT = 2 x RFB x IFS The maximum and minimum single-ended voltages out of the amplifier are, respectively, To keep the pin count reasonable, these auxiliary DACs each share a pin with the corresponding FSADJx resistor. They are, therefore, usable only when enabled and when that DAC is operated on its internal full-scale resistors. A simple I-to-V converter is implemented on chip with selectable shunt resistors (3.2 k to 16 k) such that if REFIO is set to exactly 1 V, REFIO/2 equals 0.5 V and the following equation describes the no load output voltage:
1 .5 16 k VOUT = 0.5 V - I DAC - RS
R VMAX = VREF x 1 + FB RB
VMIN = VMAX - RFB x IFS

Figure 92 illustrates the function of all the SPI bits controlling these DACs with the exception of the QAUXEN and IAUXEN bits and gating to prohibit RS < 3.2 k.
RNG0 RNG1 AUXDAC [9:0] (OFS > 4 = 4) AVDD RNG: 00 = > 125A fS 01 = > 62A fS 10 = > 31A fS 11 = > 16A fS
The common-mode voltage of the differential output is determined by the formula VCM = VMAX - RFB x IFS
CF RB RFB
OFS2 OFS1 OFS0
16k 4k 8k 16k 16k
AUX PIN
-
OP AMP
AD9714/AD9715/ AD9716/AD9717
IOUTP 28
RS
+ -
ADA4841-2
07265-043
REFIO 2
REFIO 34 C RS
+
VOUT
Figure 92. AUXDAC Simplified Circuit Diagram
IOUTN 29
ADA4841-2
07265-061
RB
Figure 91. Single-Supply Differential Buffer
AUXILIARY DACs
The DACs of the AD9714/AD9715/AD9716/AD9717 feature two versatile and independent 10-bit auxiliary DACs suitable for dc offset correction and similar tasks. Because the AUXDACs are driven through the SPI port, they should never be used in timing-critical applications, such as inside analog feedback loops.
OUTPUT (V)
0
10
20
30
40
50 60 70 80 IAUXDAC (A)
90
100 110 120 130
Figure 93. AUXDAC Op Amp Output vs. Current, AVDD = 3.3 V No Load, AUXDAC 0x1FF to 0x000
Rev. 0 | Page 44 of 48
07265-045
+ -
CF RFB
AVSS 25
The SPI speed limits the update rate of the auxiliary DACs. The data is inverted such that IAUXDAC is full scale at 0x000 and zero at 0x1FF, as shown in Figure 93.
3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 R_OFFSET R_OFFSET R_OFFSET R_OFFSET R_OFFSET = 3.3k = 4k = 5.3k = 8k = 16k OP AMP OUTPUT VOLTAGE vs. CHANGES IN R_OFFSET AND IDAC
AD9714/AD9715/AD9716/AD9717
Two registers are assigned to each DAC with 10 bits for the actual DAC current to be generated, a 3-bit offset (and gain) adjustment, a 2-bit current range adjustment, and an enable/ disable bit. Setting the QAUXOFS and IAUXOFS bits to all 1s disables the respective op amp and routes the DAC current directly to their respective FSADJI/ AUXI or FSADJQ/AUXQ pins. This is especially useful where the loads to be driven are beyond the limited capability of the on-chip amplifier. The DAC output will open circuit when not enabled (QAUXEN or IAUXEN = 0).
AD9714/AD9715/ AD9716/AD9717
I OR Q DAC
AD9714/AD9715/ AD9716/AD9717 AUXDAC OPTIONAL PASSIVE FILTERING 1k ADL537x FAMILY I OR Q INPUTS
100k
07265-063
Figure 95. Typical Use of Auxiliary DACs When DC Coupling to Quadrature Modulator ADL537x Family
DAC-TO-MODULATOR INTERFACING
The auxiliary DACs can be used for local oscillator (LO) cancellation when the DAC output is followed by a quadrature modulator. This LO feedthrough is caused by the input referred dc offset voltage of the quadrature modulator (and the DAC output offset voltage mismatch) and can degrade system performance. Typical DAC-to-quadrature modulator interfaces are shown in Figure 94 and Figure 95. Often, the input common-mode voltage for the modulator is much higher than the output compliance range of the DAC, so that ac coupling or a dc level shift is necessary. If the required common-mode input voltage on the quadrature modulator matches that of the DAC, the dc blocking capacitors in Figure 94 can be removed. A low-pass or band-pass passive filter is recommended when spurious signals from the DAC (distortion and DAC images) at the quadrature modulator inputs can affect the system performance. Placing the filter at the location shown in Figure 94 and Figure 95 allows easy design of the filter, because the source and load impedances can easily be designed close to 500 for a 2 mA full-scale output.
MODULATOR V+
CORRECTING FOR NONIDEAL PERFORMANCE OF QUADRATURE MODULATORS ON THE IF-TO-RF CONVERSION
Analog quadrature modulators make it very easy to realize single sideband radios. However, there are several nonideal aspects of quadrature modulator performance. Among these analog degradations are gain mismatch and LO feedthrough.
Gain Mismatch
The gain in the real and imaginary signal paths of the quadrature modulator may not be matched perfectly. This leads to less than optimal image rejection because the cancellation of the negative frequency image is less than perfect.
LO Feedthrough
The quadrature modulator has a finite dc referred offset, as well as coupling from its LO port to the signal inputs. These can lead to a significant spectral spur at the frequency of the Quadrature Modulator LO. The AD9714/AD9715/AD9716/AD9717 have the capability to correct for both of these analog degradations. However, understand that these degradations drift over temperature; therefore, if close to optimal single sideband performance is desired, a scheme for sensing these degradations over temperature and correcting them may be necessary.
AD9714/AD9715/ AD9716/AD9717
I DAC
AD9714/AD9715/ AD9716/AD9717 AUXDAC1
OPTIONAL PASSIVE FILTERING
QUADRATURE MODULATOR I INPUTS
I/Q CHANNEL GAIN MATCHING
100k MODULATOR V+
AD9714/AD9715/ AD9716/AD9717
Q DAC
AD9714/AD9715/ AD9716/AD9717 AUX2DAC
OPTIONAL PASSIVE FILTERING
QUADRATURE MODULATOR Q INPUTS
100k
07265-062
Figure 94. Typical Use of Auxiliary DACs and On-Chip Resistors for Direct Coupling to Quadrature Modulators
Fine gain matching is achieved by adjusting the values in the DAC fine gain adjustment registers. For the I DAC, these values are in the I DAC gain register (Register 0x03). For the Q DAC, these values are in the Q DAC gain register (Register 0x06). These are 6-bit values that cover 2% of full scale. To perform gain compensation starting from the default values of zero, raise the value of one of these registers a few steps until it can be determined if the amplitude of the unwanted image is increased or decreased. If the unwanted image increased in amplitude, remove the step and try the same adjustment on the other DAC control register. Iterate register changes until the rejection cannot be improved further. If the fine gain adjustment range is not sufficient to find a null (that is, the register goes full scale with no null apparent) adjust the course gain settings of the two DACs accordingly and try again. Variations on this simple method are possible.
Rev. 0 | Page 45 of 48
AD9714/AD9715/AD9716/AD9717
Note that LO feedthrough compensation is independent of phase compensation. However, gain compensation can affect the LO compensation because the gain compensation may change the common-mode level of the signal. The dc offset of some modulators is common-mode level dependent. Therefore, it is recommended that the gain adjustment be performed prior to LO compensation.
5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 447.5
LO FEEDTHROUGH COMPENSATION
To achieve LO feedthrough compensation in a circuit, each output of the two AUXDACs must be connected through a 100 k resistor to one side of the differential DAC output. See the Auxiliary DACs section for details of how to use AUXDACs. The purpose of these connections is to drive a very small amount of current into the nodes at the quadrature modulator inputs, therefore adding a slight dc bias to one or the other of the quadrature modulator signal inputs. To achieve LO feedthrough compensation, the user should start with the default conditions of the AUXDAC registers, then increment the magnitude of one or the other AUXDAC output voltages. While this is being done, the amplitude of the LO feedthrough at the quadrature modulator output should be sensed. If the LO feedthrough amplitude increases, try either decreasing the output voltage of the AUXDAC being adjusted, or try adjusting the output voltage of the other AUXDAC. It may take practice before an effective algorithm is achieved. Using the AD9714/AD9715/AD9716/AD9717 evaluation board, the LO feedthrough can typically be adjusted down to the noise floor, although this is not stable over temperature.
(dB)
449.0
450.0 FREQUENCY (MHz)
451.0
452.5
Figure 96. AD9714/AD9715/AD9716/AD9717 and ADL5370 with a SingleTone Signal at 450 MHz, No Gain or LO Compensation
5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 447.5
(dB)
449.0
450.0 FREQUENCY (MHz)
451.0
452.5
RESULTS OF GAIN AND OFFSET CORRECTION
The results of gain and offset correction can be seen in Figure 96 and Figure 97. Figure 96 shows the output spectrum of the quadrature demodulator before gain and offset correction. Figure 97 shows the output spectrum after correction. The LO feedthrough spur at 450 MHz has been suppressed to the noise level. This result can be achieved by applying the correction, but the correction needs to be repeated after a large change in temperature. Note that gain matching improves the negative frequency image rejection, but it is also related to the phase mismatch in the quadrature modulator. It can be improved by adjusting the relative phase between the two quadrature signals at the digital side or properly designing the low-pass filter between the DACs and quadrature modulators. Phase mismatch is frequency dependent, so routines have to be developed to adjust it if wideband signals are desired.
Figure 97. AD9714/AD9715/AD9716/AD9717 and ADL5370 with a SingleTone Signal at 450 MHz, Gain and LO Compensation Optimized
Rev. 0 | Page 46 of 48
07265-065
07265-064
AD9714/AD9715/AD9716/AD9717
MODIFYING THE EVALUATION BOARD TO USE THE ADL5370 ON-BOARD QUADRATURE MODULATOR
The evaluation board contains an Analog Devices, Inc., ADL5370 quadrature modulator. The AD9714/AD9715/ AD9716/AD9717 and the ADL5370 provide an easy-tointerface DAC/modulator combination that can be easily characterized on the evaluation board. Solderable jumpers can be configured to evaluate the single-ended or differential outputs of the AD9714/ AD9715/AD9716/AD9717. This is the default configuration from the factory and consists of the following population of the components: * * * JP55, JP56, JP76, JP82--unsoldered R13, R14, R52, R53--unpopulated R50, R57, T1, T2--populated To evaluate the ADL5370 on this board, the population of these same components should be reversed so that they are in the following positions: * * * JP55, JP56, JP76, JP82--soldered R13, R14, R52, R53--populated R50, R57, T1, T2--unpopulated
The AUXDAC outputs can be connected to Test Point TP44 and Test Point TP45 if LO feedthrough compensation is necessary.
Rev. 0 | Page 47 of 48
AD9714/AD9715/AD9716/AD9717 OUTLINE DIMENSIONS
6.00 BSC SQ 0.60 MAX 0.60 MAX
31 30 40 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
5.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
EXPOSED PAD
(BOT TOM VIEW)
4.25 4.10 SQ 3.95
10
21 20
11
0.25 MIN 4.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 98. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm x 6 mm, Very Thin Quad (CP-40-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9714BCPZ 1 AD9714BCPZRL71 AD9715BCPZ1 AD9715BCPZRL71 AD9716BCPZ1 AD9716BCPZRL71 AD9717BCPZ1 AD9717BCPZRL71 AD9714-EBZ1 AD9715-EBZ1 AD9716-EBZ1 AD9717-EBZ1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ Evaluation Board Evaluation Board Evaluation Board Evaluation Board
Package Option CP-40-1 CP-40-1 CP-40-1 CP-40-1 CP-40-1 CP-40-1 CP-40-1 CP-40-1
Z = RoHS Compliant Part.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07265-0-8/08(0)
Rev. 0 | Page 48 of 48
072108-A
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

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